The present invention relates generally to synchronous electronic systems, and more particularly to generating and distributing synchronous clocks across a system to provide a reliable synchronous clock with a precise duty cycle.
Clocks used for providing timing at multiple locations in a synchronous system, such as, for example, in an electronic circuit board configured as a backplane, must have a precisely controlled phase relationship and accurate duty cycle (e.g., fifty percent duty cycle) to provide proper operation. Specifically, if a proper phase relationship is not provided with respect to control (i.e., clocking) signals used to control different components of the system, the system will be unable to provide proper operation, and in particular, the data output may not be valid (i.e., unreliable). For example, the signals provided at different locations within the system may be out of phase because of differences in timing during power up initialization, due to jitter, or electronic noise.
Known systems attempt to solve the problem of non-synchronized control signals provided at various locations within a system using T-type type flip-flops or similar digital logic circuits. These flip-flops include a single input, to which a clocking signal is applied to trigger the output between two states (i.e., high and low). However, because power cannot be reliably provided to the various T-type flip-flops in the system (i.e., power turned on at different times), the clock signals at the various locations may be out of phase with each other. Once the signals are out of phase, the system must be reset (i.e., reset all clock signals to flip-flops to provide a known state) in order to synchronize the signals. Further, every time a new T-type flip-flop in the system is activated (i.e., powered up) it is not possible to determine the initial state of the clock of that specific T-type flip-flop. Thus, again, synchronization is not ensured until the system is reset.
Therefore, in these systems, a reset of the T-type flip-flops must be provided each time a glitch occurs, which is not always detected. Further, a reset of the clocking signal to all the T-type flip-flops must be provided on any power restart. An external reset may be used to set all clocks to the same state. However, this adds complications (i.e., control issues) and limitations to the system, as well as cost. Additionally, these known systems require that the reference clock provide a precision duty cycle source (e.g., 50 percent duty cycle) for proper operation. For example, in systems requiring high data transfer rates, both edges of the clock signal are required to gate the data, requiring a precise duty cycle source.
Thus, there exists a need to provide a reliable synchronous clock signal across a system (e.g., clock distribution across a backplane), particularly in a system requiring gating of higher speed data. Further, a precise synchronous clock having a reliable duty cycle must be provided to various locations within the system (i.e., synchronous local clock).
This present invention provides a device and method for generating a precisely controlled clock signal (i.e., phase and duty cycle) for use in multiple locations within a system, to thereby provide proper operation. For example, in systems requiring high data transfer rates, precision synchronized fifty percent duty cycle clocks at multiple locations within a system are required for proper operation.
Specifically, in one preferred embodiment of the present invention, a control device is provided to allow for synchronized clocking in multiple locations of a system to thereby provide synchronous operation. The control device includes a first input means for receiving a phase reference signal, a second input means for receiving a clock signal, and an output means for providing an output signal based upon the phase reference signal when triggered by the clock signal. The clock signal includes a specific active transition (i.e., active edge) and the output means is preferably triggered by the active transition of the clock signal, and changes its output if the phase reference signal at the active edge has changed from the last active transition. In systems requiring a precise duty cycle (e.g., 50% duty cycle), such as, for example, systems having high data transfer rates needing a precise 50% duty cycle, or a system using both edges of the clock (i.e., a two phase clocked system), the phase reference signal may be configured at one-half the frequency of the clock signal.
The control device may be constructed as a digital logic circuit, such as, for example, an input flip-flop, and more specifically, a D-type flip-flop that is provided at each location in the system requiring a synchronous clock. In this construction, the first input means is configured as a data input of a D type flip-flop and the second input means is configured as a clock input of a D type flip-flop. Further, the flip-flop may have a hold time and wherein a phase relationship between the signals received at the first and second input means is not more than the period of the clock input signal minus the hold time. Further, the phase relationship of output signals based upon the same phase and clock input signals (i.e., with respect to other generated output signals) is determined by the relative transmission line length to the second input means.
In another preferred embodiment of the present invention, a system having a plurality of components in different locations requiring synchronized timing is provided. The synchronous system includes a clock generating means for providing a clock signal, a phase reference generating means for providing a phase reference signal, and a timing means provided at each of the components for synchronizing operation of the components. In particular, the timing means is configured for receiving the clock signal and the phase reference signal and outputting a control signal having a frequency based upon the received clock signal and the phase reference signal. Specifically, the timing means is configured to be triggered by an active transition (i.e., active edge) of the clock signal to thereby provide the control signal.
The phase reference signal and clock signal are preferably each configured at a predetermined frequency (i.e., phase and clock synchronized at some frequency or multiple thereof) and the timing means is adapted to output the control signal based upon the relationship between the phases. In systems requiring a precise duty cycle, such as, for example, systems having high-speed data transfer requiring a precise fifty percent duty cycle, the phase signal is provided at a frequency that is one-half of the clock signal, thus providing a 50% duty cycle. The timing means is configured to provide the control signal to the components to thereby define a duty cycle.
The timing means may be constructed as any suitable digital logic circuit, such as, for example, a flip-flop. In particular, in this construction, the timing means may comprise a D-type flip-flop with a data input adapted for receiving the phase reference signal and a clock input adapted for receiving the clock signal and triggering the D-type flip-flop to provide the control signal based upon the clock signal.
In yet another preferred embodiment of the present invention a method of providing synchronized clocking to multiple locations within a system includes providing a synchronized phase reference signal to the multiple locations, providing a synchronized clock signal to the multiple locations, and outputting a control signal based upon the synchronized phase reference signal triggered by the clock signal. The outputting may be triggered by an active transition (i.e., active edge) of the clock signal.
Each of the phase reference signal and clock signal may have a predetermined frequency (i.e., synchronous signals to provide 50% duty cycle and determined by clock input) and wherein the method further includes configuring the predetermined frequencies to obtain a specific duty cycle. In systems requiring a precise duty cycle, such as a fifty percent duty cycle in high data transfer rate systems, the phase reference signal is provided at one-half the frequency of the clock signal.
The method may include using a D-type flip-flop to receive the synchronized phase reference signal and synchronized clock signal and provide the step of outputting. Further, the step of using a D-type flip-flop may include using a D-type flip-flop at each of the multiple locations requiring local synchronized clocking.
Thus, the present invention provides a device and method for reliably synchronizing various components within a system that may require a precise duty cycle. Using two clocking signals, the present invention ensures synchronized timing that is in phase.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.